The speed, power, and complexity of integrated circuits (ICs), such as application specific integrated circuit (ASIC) chips, central processing unit (CPU) chips, digital signal processor (DSP) chips and the like, have greatly increased in recent years. These advancements have made possible the development of system-on-a-chip (SOC) devices, among other things. A SOC device integrates into a single chip all (or nearly all) of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a television receiver, and the like). Advanced semiconductor process technologies allow these circuits to be fabricated as dense high performance integrated circuit.
Power dissipation is an important constraint in such dense high performance integrated circuits. A combination of several power minimization techniques is used to keep the power dissipation of chips within bounds. One such technique involves adapting the clock frequency of a circuit to the performance requirement of the system. When higher system throughput is desired, the clock frequency is increased dynamically. The clock frequency is lowered when the throughput requirement is lower to reduce power dissipation of the circuit.
Dynamic control of the system clock frequency may be achieved in two ways, namely:                1) Continuously variable clock frequency: In this technique, the clock frequency of the system can be gradually changed to a new value without stopping the clock. This technique is used in conjunction with voltage scaling techniques and requires analog circuits; and        2) Discretely variable clock frequency: In this technique, the system can operate at only a few predetermined clock frequencies. The transition to a new clock frequency is possible only in discrete steps. To avoid corruption of data stored in the system, the clock to the system must be stopped before the transition from a first clock source to a second clock source is made (i.e., the transition from one clock domain to another must be “glitchless”). An important advantage in using this technique is that the clocks may be switched using digital circuits.        
Therefore, there is a need in the art for an improved clock selection circuit for applying a selected one of two clock sources to a clock circuit, such as a data processor.